The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies advance, chip-scale or chip-size packaging based semiconductor devices have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a chip-scale packaging based semiconductor device, the packaging is generated on the die with contacts provided by a variety of bumps. Much higher density can be achieved by employing chip-scale packaging based semiconductor devices. Furthermore, chip-scale packaging based semiconductor devices can achieve smaller form factors, cost-effectiveness, increased performance, lower power consumption and lower heat generation.
In order to increase manufacturing efficiency and lower manufacturing cost, integrated circuits may be manufactured in semiconductor wafers, each containing many identical semiconductor chips. Once the integrated circuits have been manufactured, a dicing process may be applied to the semiconductor wafers. As a result, semiconductor chips are sawed from the wafers.
In a packaging process, semiconductor chips may be attached to a package substrate. The fabrication steps of the packaging process may comprise securing the semiconductor chips on the package substrate and connecting bond pads on the semiconductor chips to bond pads on the package substrate. Furthermore, an underfill layer may be employed to further secure the bonding between the semiconductor chips and the package substrate.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.